1. Technical Field
The present invention relates to a metal silicide self-aligned SiGe heterojunction bipolar transistor and a method of forming the same.
2. Description of Related Art
Planar silicon (Si) bipolar transistors are conventional devices for constructing analog integrated circuits (ICs). However, because silicon materials are inherently disadvantageous in speed, group III-V compound (e.g., gallium arsenide) semiconductor devices have always dominated in the field of high-frequency and high-speed applications in the history. For SiGe heterojunction bipolar transistors obtained by introducing narrow-bandgap SiGe alloys into silicon bipolar transistors as materials of base regions, not only the high-frequency performance is improved significantly but also the advantage of the low cost of the silicon-based technology is maintained. Therefore, the SiGe heterojunction bipolar transistors have been widely used in the field of radio frequency (RF), microwave and high-speed semiconductor devices and ICs, and have partially replaced the compound (e.g., gallium arsenide) semiconductor technologies.
The base resistance RB and the collector-base capacitance CBC of a bipolar transistor have always been primary parasitic parameters that restrict further improvement of the high-frequency performance of the device, and the influence of the base resistance RB and the collector-base capacitance CBC on the high-frequency performance index of the device can be described by using the following simplified expression:
      f          ma      ⁢                          ⁢      x        =                    f        T                    8        ⁢        π        ⁢                                  ⁢                  R          B                ⁢                  C          BC                    where fT and fmax represent the cut-off frequency and the maximum oscillation frequency of the device respectively.
Furthermore, the base resistance RB is also the primary source of thermal noises of the bipolar transistor. Therefore, in order to improve the high-frequency performance and the noise performance of the device, reducing the base resistance RB is always one of important tasks for optimization of bipolar transistor devices and processes.
One of effective means to reduce the base resistance RB is to use the emitter region-extrinsic base region self-aligned structure (i.e., to ensure that the space between the heavily doped extrinsic base region and the emitter region of the device is not determined by and is generally much smaller than the minimum line width or the minimum overlay space permitted by photolithography).
For a heterojunction bipolar transistor with the SiGe base region formed through an epitaxy growth process, the device structure with a self-aligned elevated extrinsic base region satisfies the requirements of self-alignment between the heavily doped extrinsic base region and the emitter region and, thus, becomes a standard device structure for the current high-performance self-aligned SiGe heterojunction bipolar transistor process. Processes for achieving such a device structure with the self-aligned elevated extrinsic base region may be generally divided into two kinds One kind features that the self-aligned elevated extrinsic base region is formed after the intrinsic base epitaxy growth, with the self-aligned architecture achieved mainly with help of some sort of planarization process. The other kind of process achieves such a device structure in the following way: firstly, depositing a heavily doped polycrystalline elevated extrinsic base region; then, opening the emitter window through photolithography and etching; finally, growing a intrinsic base epitaxial layer inside the formed emitter window through a selective epitaxy process, joining the intrinsic base epitaxial layer with the polycrystalline cantilevers of the pre-formed heavily doped elevated extrinsic base region.
The above two kinds of technical solutions have a common shortcoming that the processes are complex. The former technical solution requires use of expensive special planarization apparatuses and processes; and the latter technical solution may cause process quality control problems (e.g., some defects such as voids may be formed in the linkup base region between the pre-formed extrinsic base region and the intrinsic base region that is grown through the selective epitaxy process) because the intrinsic base region playing a decisive role in the device performance need be grown through the selective epitaxy process which is difficult to control. Therefore, up to now, the device structure of the SiGe heterojunction bipolar transistor with a self-aligned elevated extrinsic base region and the process of forming the same still need be improved.